Chapter 8. Timing Distribution & BITS (Building Integrated Timing Supply) Clock Considerations

Definition

Synchronization networks provide timing signals to all synchronization network elements at each node in a digital network. These timing signals are traceable to a highly accurate Primary Reference Source (PRS) clock of Stratum 1 quality. The aim is to ensure that all outgoing transmissions from a digital network node have the same average frequency. Buffer elements are used at important transmission interfaces to absorb differences between the average local frequency and the actual short-term frequency of incoming signals, which may be affected by phase wander and jitter accumulated along the transmission paths.

A sync network has two major parts: interoffice and intraoffice. The interoffice network consists of a primary and a secondary DS1 link, carrying timing between offices in a hierarchical relationship. Intraoffice timing distribution is based on the concept of a BITS master clock, providing timing to all other digital equipment in the office. A BITS clock system is shown in Figure 6 [References 2 and 3]. The Larus STS 5400 and STS 5800 Systems are examples of BITS clocks.

Interoffice Distribution

Timing information is distributed to offices through a hierarchical series of levels, starting with a PRS (see Figure 3). Clocks are grouped into stratum levels, based on their ability to maintain accurate timing if their reference fails (holdover mode). Stratum 1 is the most accurate; it is by definition a stand-alone PRS, which does not have an external reference. Stratum 4 clocks are the least accurate; they have no holdover requirements and are typically found in DS1 terminal equipment, such as D4 channel banks.

A given clock must be able to track a reference from a free-running clock of the same or higher stratum level. BITS clocks in central offices are either Stratum 2, Stratum 3 or Stratum 3E (Larus Stratum 3E Enhanced), with Stratum 2 being used in the larger offices where holdover drift can affect hundreds or thousands of out going trunks.

A sync network is designed so that a clock always receives timing from a clock of equal or higher Stratum level. This ensures that if an upstream clock enters a hold mode, the downstream clocks will be able to track it. Stratum 2, 3E (3E Enhanced) and 3 clocks are provided with primary and secondary timing reference inputs, with automatic switching between the two if either one fails. Timing distribution is typically done with traffic-carrying DS1 signals over paths selected for best availability. However, using traffic-carrying DS1s for this purpose is discouraged when using SONET transport equipment.

The following are the major rules used in designing a sync network [References 3 and 7]:

A. An office BITS clock can receive its reference only from another office or offices of the same or higher stratum level. A higher stratum is preferred, provided reliable diverse DS1 paths from that office exist, but is not necessary.

B. For a given BITS clock, a DS1 facility with the highest availability should be selected for the primary reference input from an upstream clock. A facility with the next highest availability should be selected for the secondary reference, preferably on a diverse route from a different upstream clock. The availability of a path is determined by its historical failure record, installation or rearrangement activity, facility length and type, protection switching, and the number of repeaters or multiplexers on the path. There may be specific equipment types that must be avoided.

C. No timing loops are allowed in the sync network for any combination of primary and secondary facilities. The potential for loops exist when either primary or secondary reference signals are passed between clocks of the same stratum. Loops are avoided within an office by distributing timing from the BITS clock in a star network. SONET rings, at present, cannot operate with redundant timing, as they are by definition a loop. The solution to this dilemma is the use of synchronization messaging, which is to be implemented by all vendors in their SONET timing and transmission equipment, once a standard for these messages has been approved in the T1X1 and T1E1 committees.

D. There are no fixed rules for the number of BITS clocks that can be used in cascade. Any clock can track any other clock of equal or higher stratum level, and it will filter out most jitter and short-term wander introduced along the timing reference path. However, long-term wander (over periods of hours) and possible phase transients will accumulate along the cascaded paths from the PRS to a given clock. Furthermore, the failure of a reference path will affect all downstream clocks. For these reasons, the number of cascaded clocks should be minimized as far as possible, and be consistent with the use of whatever highly reliable reference paths are available in the network. As an example, it would be preferable to time a Stratum 3 clock from another Stratum 3 clock upstream, which is in turn timed from a Stratum 2 clock through reliable facilities, rather than use a direct path of questionable reliability to that Stratum 2 clock. The objective should be to maximize the overall availability.

E. Reference 3 recommends that no more than two Stratum 3 or 3E offices be timed in tandem, and where possible, the timing distribution should be limited to only one Stratum 3 office. This reference applies to large Telco synchronization networks.

Intraoffice Distribution

The BITS clock system is the preferred method of distributing timing within an office. Redundant hardware, and automatic switching between primary and secondary reference inputs, provide a high degree of availability. The BITS clock supplies timing directly to all digital equipment in the office requiring synchronization, usually by means of DS1 framed ones, or a 64 kb Composite Clock. Many network elements have primary and secondary timing ports; the signals to these should be taken from different output cards of the BITS system. The BITS clock may also provide primary and secondary timing signals, through interoffice sync network paths specially selected for high availability, to other BITS clocks in downstream offices.

SONET, Extensions to the Rules

Some of the more important considerations for synchronizing SONET network elements (NEs), which are still evolving, are as follows [References 6 and 7]:

A. External timing for SONET NEs from a BITS clock is the preferred mode, where BITS is available.

B. When BITS timing is not available, other SONET timing modes (line, through or loop timing) should be chosen in such a way as to avoid timing loops and to minimize the lengths of timing paths. Rings may only be fed in one direction with a single reference.

C. If a string of more than one SONET add-drop multiplexers (ADM) exists between BITS timed offices, no secondary references should be used. This also applies to ring configurations; timing should be passed in one direction only, between line-timed ADMs. This guideline applies until synchronization messages, now under discussion in the T1X1 committee, can be implemented.

D. Be cautious about using DS1s carried on SONET for synchronization distribution. These DS1s are subject to phase transients (pointer adjustments) which may not meet short term stability requirements. However, Larus 3E Enhanced clocks have been shown to tolerate the traffic-carrying adjustments and filter out the short term variations. It may be necessary to pass timing this way, because customers may have no other choice of a timing source.

E. SONET NEs may have the capability of deriving a DS1 timing signal which is not part of the payload, but is locked to the incoming OC-N line rate. This can be used for sync distribution; however it is recommended that sync not be passed in this way along a route that has line or through timed ADMs, until sync messages are implemented. The downstream NE, at present, has no way of knowing whether the intermediate ADM might have a receive failure and be running on its internal clock. The internal SONET maintenance clock is +/-20 ppm, and has no holdover capability.